View CP2120_7485406.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0.4 4/09 copyright ? 2009 by silicon laboratories CP2120 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. CP2120 spi to i 2 c b ridge and gpio p ort e xpander single chip spi to i 2 c transfer ?? integrated clock; no external clock required ?? on-chip voltage monitor slave serial peripheral interface (spi) ?? up to 1.0 mbit/s transfers ?? configurable to least significant bit or most significant bit first byte transfers i 2 c master interface ?? operates at configurable rates up to 400 khz ?? 255 rx and tx data buffers input and output port pins ?? 8 pins configurable as push-pull or open-drain ?? 1 pin configurable as an edge-triggered interrupt source ?? all pins 5 v tolerant ?? int active low interrupt pin supply voltage of 2.7 v to 3.6 v ?? typical operating current: 6.4 ma package ?? pb-free 20-pin qfn figure 1. block diagram voltage monitor internal oscillator controller i 2 c interface port controller internal registers spi interface eight i/o pins edge-triggered interrupt source sda scl miso mosi sck cs
CP2120 2 rev. 0.4
CP2120 rev. 0.4 3 t able o f c ontents section page 1. system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. global dc electri cal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4. pinout and package defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.1. pin out chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.2. qfn-20 pinout diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.3. qfn-20 pinout diagram (b ottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.4. qfn-20 solder paste recommendatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5. spi slave bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5.1. command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2. internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 5.3. spi byte orientati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4. spi timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5. i 2 c activity during spi transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 6.1. determining pull-up register valu es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2. i 2 c internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3. i 2 c status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4. i 2 c receive buffer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5. i 2 c commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. port i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. CP2120 revision number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CP2120 4 rev. 0.4 1. system overview the CP2120 is a highly-integrated spi-to-i 2 c bridge controller with an spi interface that provides a simple and reliable method for communicating with i 2 c devices. the CP2120 includes a 4-wire serial peripheral interface (spi), a serial i 2 c interface, 256 byte data buffers, an internal o scillator, eight input/out put port pins, and one pin configurable as an edge-triggered interrupt source in a compact 4x4 package. no external components other than pull-up resisters on the i 2 c pins are required. the spi master controls the CP2120 across the spi interface using a command set that governs all CP2120 configuration and operation. 2. absolute maximum ratings 3. global dc electrical characteristics table 1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd or gnd ? ? 500 ma maximum output current sunk by rst or any port pin ??100ma note: stresses above the absolute maximum ratings may cause perman ent device damage. this is a stress rating only, and functional operation of the devices at any conditions equal to or greater than thos e indicated in the operational listings of this specification are not implied. exposure to maxi mum rating conditions for extended periods may affect device reliability. table 2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage v rst 3.0 3.6 v digital supply current v dd =3.0 v ?3.84.1ma specified operating temperature range ?40 ? +85 c
CP2120 rev. 0.4 5 4. pinout and package definition 4.1. pin out chart name pin # type description v dd 3 power supply pin gnd 2 ground rst 4 digital i/o device reset. open -drain output of internal por or vdd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. sclk 1 digital in spi clock input miso 20 digital out spi slave output mosi 19 digital in spi slave input cs 18 digital in spi slave select sda 17 digital i/o i 2 c data input/output scl 16 digital i/o i 2 c clock input/output gpio 0 5 digital i/o general purpose configurable digital input/output gpio 1 12 digital i/o general purpose configurable digital input/output gpio 2 11 digital i/o general purpose configurable digital input/output gpio 3 10 digital i/o general purpose configurable digital input/output gpio 4 9 digital i/o general purpose configurable digital input/output gpio 5 8 digital i/o general purpose configurable digital input/output gpio 6 7 digital i/o general purpose configurable digital input/output gpio 7 6 digital i/o general purpose configurable digital input/output eint 13 digital i/o edge-triggered interrupt source int 14 digital out CP2120 interrupt indicator nc 15 digital out not connected, leave floating
CP2120 6 rev. 0.4 4.2. qfn-20 pinout diagram (top view) 3 4 5 1 2 8 9 10 6 7 13 12 11 15 14 18 19 20 16 17 sclk gnd vdd rst gpio 0 gpio 7 gpio 6 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 eint int nc scl sda cs mosi miso CP2120 gnd
CP2120 rev. 0.4 7 4.3. qfn-20 pinout di agram (bottom view) table 4.1. qfn-20 package dimensions mm min typ max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 0 0.65 1.00 a3 ? 0.25 ? b 0.18 0.23 0.30 d?4.00? d2 2.00 2.15 2.25 e?4.00? e2 2.00 2.15 2.25 e?0.5? l 0.45 0.55 0.65 n?20? nd ? 5 ? ne ? 5 ? r0.09? ? aa ? 0.435 ? bb ? 0.435 ? cc ? 0.18 ? dd ? 0.18 ?
CP2120 8 rev. 0.4 4.4. qfn-20 solder paste recommendations
CP2120 rev. 0.4 9 5. spi slave bus the CP2120 provides a four-wire slave spi interface. the CP2120's spi bus activates whenever the spi master pulls the nss pin low. the master can then clock data into the CP2120 through the master-out-slave-in (mosi) pin and receive data from the CP2120 through the master -in-slave-out (miso) pin. the spi master provides the spi with a clock source. figure 2 show s typical connections for an spi bus. figure 2. spi bus typical connections sclk should be held high when idle. figure 3 shows a cp 2120 data transfer on the spi bus. if the CP2120 is the only slave device on the spi bus, the nss pin can be tied low. figure 3. slave mode data/clock timing miso mosi spiclk cs sclk cs CP2120 spi master msb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sck mosi miso nss
CP2120 10 rev. 0.4 5.1. command set an spi master controls the CP2120 by sending commands across the spi bus. some commands initiate i 2 c transactions, while other commands modify or monitor CP2120 operation and events. 5.2. internal registers the CP2120 maintains a set of internal registers that ca n be modified to configure general purpose port i/o and i 2 c operation and can be read to obtain device status. command s reading to and writing from the internal registers can be issued at any time, even while an i 2 c transaction is in progress, as they do not initiate any i 2 c bus transactions. table 3 shows a list of all internal registers. 5.2.1. write to internal register a write to internal register command updates the value of one of the CP2120's internal registers. a write to internal register command begins with the command byte, 0x20, followed by the internal register address, followed by the new value of the internal regi ster. only one register can be accessed per write to internal register command. table 3. internal register addresses internal register address section ioconfig 0x00 7. iostate 0x01 7. i2cclock 0x02 6.1 i2cto 0x03 6.1 i2cstat 0x04 6.2 i2cadr 0x05 6.1 rxbuff 0x06 6.3 ioconfig2 0x07 7. edgeint 0x08 7. i2cto2 0x09 6.1 0x20 command register x data byte spi master
CP2120 rev. 0.4 11 5.2.2. read from internal register a read from internal register command retrieves the current value of one of the CP2120's internal registers. the command begins with the command byte, 0x21, followed by t he internal register address. this byte is followed by the transmission of a "don't care" by te, which can be of any value and is ignored by the CP2120. after the "don't care" byte, the internal register valu e is transmitted across the miso line. 5.3. spi byte orientation the spi configuration command configures the bit orientation of trans fers across the spi bus to one of two states. if spi transmits most-significant-bit first, bit 7 is transmitte d first. if spi transmits least-significant-bit first, bit 0 is transmitted first. 5.3.1. spi configuration the command begins with the command byte (0x18), followed by spi configuration byte, which should equal one of the values shown in the following table. any values other than those listed in the table are ignored. 5.4. spi timing diagrams figure 4. spi slave timing byte value configuration 0x81 most significant bit first 0x42 least significant bit first command 0x21 register address don?t care spi master CP2120 register data command 0x18 spi configuration spi master nss sck* mosi miso t sez t soh t sih t sis t ckh t se t ckl t sd t slh t sdz
CP2120 12 rev. 0.4 5.5. i 2 c activity during spi transactions if the spi master attempts to transmit a command to the CP2120 while the i 2 c bus is inactive, the CP2120 will disable its slave response. if an i 2 c master device on the bus attempts to address the CP2120 during this time, the CP2120 will not ack the addr ess defined in the i2ca dr internal register. if the spi master attempts to transmit a command to the CP2120 while the CP2120 is acting as the master on the i 2 c bus, the CP2120 will suspend i 2 c bus activity until the spi master has completed transmission of the command. for instance, if the spi mast er calls the read internal register command while the CP2120 is in the middle of an i 2 c transaction, that i 2 c transaction will stall until the CP2120 completely processes the read internal register command. table 4. spi slave timing parameters slave mode timing * (see figure 4) t se nss falling to first sclk edge 2xt sysclk ?ns t sd last sclk edge to nss rising 2xt sysclk ?ns t sez nss falling to miso valid ?4xt sysclk ns t sdz nss rising to miso high-z ?4xt sysclk ns t ckh sclk high time 5xt sysclk ?ns t ckl sclk low time 5xt sysclk ?ns t sis mosi valid to sclk sample edge 2xt sysclk ?ns t sih sclk sample edge to mosi change 2xt sysclk ?ns t soh sclk shift edge to miso change ?4xt sysclk ns t slh last sclk edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns *note: t sysclk equals 24.5 mhz.
CP2120 rev. 0.4 13 6. i 2 c serial interface the CP2120 provides an i 2 c interface able to transfer data at frequenc ies up to 400 khz. duri ng a transaction, the CP2120, operating as the i 2 c master, sources a data clock on the scl pi n as data travels across the bidirectional sda pin to and from an i 2 c slave device. the i 2 c interface lines each require a pull-up resistor. figure 5 shows a typical i 2 c bus. figure 5. typical i 2 c bus* *note: vdd is defined in table 1, ?absolute maximum rating s,? on page 4. for rpu values, please see ?6.1. determining pull-up register values? . 6.1. determining pu ll-up register values logic low to logic high transitions on the scl and sd a pins, which are configured to open-drain output with external pull-ups to vdd, take the form of an exponential curve with an rc time constant, where c equals the capacitance of the bus and r equals the pull-up resistor value. i 2 c specification defines rise time as the time required for a signal level to change from vmin +0.15 v to vmax-0.15 v. by solving the exponential equation using a vmin of 0 v and a vmax of 3.3 v, the following equation can be used to find values for pull-up resistors: rise time = 3.04448 rc bus capacitance is governed by a number of factors, in cluding signal trace length and capacitance introduced by devices on the bus. 8 mm pcb signal traces on a tw o-layer board generally add 1 pf of capacitance per centimeter of trace length. to determine the amo unt of capacitance introduced to the bus by i 2 c devices, consult those devices? datasheets. th e maximum capacitance allowed before the bus violates i 2 c specification is 400 pf. rise time requirements vary depending on each connected i 2 c device?s timing requirements and the scl clock frequency. the maximum rise time allowed by the i 2 c specification is 1000 ns. 6.2. i 2 c internal registers features of the i 2 c interface are configured through the CP2120's in ternal registers. scl clock frequency is set by writing to the i2cclk internal register. the freq uency can be determined using the equation below. the i 2 c frequency configured by the i2cclock register is only an approximate frequency. actual i 2 c frequencies can vary due to conditions on the bus, such as a slave device extending the scl low time. equation 1. i 2 c clock frequency i2c-bus device CP2120 i2c-bus device v dd r pu r pu i2c-bus sda scl i 2 c clock frequency (khz) 2000 i 2 cclk --------------------- =
CP2120 14 rev. 0.4 internal register de finition 1. i2cclock: i 2 c clock frequen cy configuration the transaction time-out counter, which terminates an i 2 c transaction after a set period of time has passed, can be configured through the i2cto internal register. if the time-out counter is not enabled, the CP2120 will make only one attempt at executing an i 2 c transaction and abort if that transaction attempt fails. equation 2. cto time-out frequency internal register de finition 2. i2cto: i 2 c time out the spi master can assign an i 2 c address to the CP2120 by writing to the i2cadr internal register. setting this address is not necessary for device operation. if set, the CP2120 w ill ack this address when another i 2 c master on the bus attempts to communicate with it. the CP2120 will nack all attempts at data transf er when responding as an i 2 c slave. internal register de finition 3. i2cadr: i 2 c address internal register address: 0x02 reset value: 0xa0 bit 7-0: i2cck7-0: i 2 c clock frequency configuration value (minimum register value = 5, maximum register value = 255) r/w r/w r/w r/w r/w r/w r/w r/w i2cck7 i2cck6 i2cck5 i2cck4 i2cck3 i2cck2 i2cck1 i2cck0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 time-out frequency to 128 --------- - hz ?? = internal register address: 0x03 reset value: 0x00 bit 7-1: to6-0: time out value bit 0: ten:time out enable bit. 0: disable timer. 1: enable timer. r/w r/w r/w r/w r/w r/w r/w r/w to6 to5 to4 to3 to2 to1 to0 ten bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 internal register address: 0x05 reset value: 0x00 bit 7-bit 0: i2cad7-0: i 2 c address sets i2c bus address. r/w r/w r/w r/w r/w r/w r/w r/w i2cad7 i2cad6 i2cad5 i2cad4 i2cad3 i2cad2 i2cad1 i2cad0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0
CP2120 rev. 0.4 15 the spi2i2c provides additional smbus-related timers to enable i 2 c protocol compatibility. setting the i 2 c bus free detect enables the device to poll the smbus lines and determine when a transfer can begin. setting the scl low time out detect will cause an smbus transaction to abor t if the scl line has been held low by a device for a period of approximately 25 ms. internal register defini tion 4. i2cto2: additional i 2 c time outs 6.3. i 2 c status the CP2120 maintains an internal register, i2csta t, which describes the current status of the i 2 c interface. the i2cstat register can be read at any time. the CP2120 updates i2cstat when an i 2 c transaction begins, when an i 2 c transaction completes (suc cessfully or unsuccessfully), and when a received spi command contains errors. it is not recommended that an spi master poll the CP2120's i2cstat internal register to determine when an i 2 c transaction has completed. the spi master should instead watch for the int pin to drop low, and then read the i2cstat register to determine the i 2 c transaction results. internal register address: 0x09 reset value: 0x00 bit 1: i 2 c bus free detect 0: bus free detect disabled 1: bus free detect enabled bit 0: i 2 c scl low time out detect 0: scl low time out detect disable 1: scl low time out detect enable r/w r/w r/w r/w r/w r/w r/w r/w reserved reserved reserved rese rved reserved reserved fren lwen bit 7bit 6bit 5bit 4 bit3 bit 2bit 1bit 0
CP2120 16 rev. 0.4 internal register definition 5. i2cstat: i 2 c status register internal register address: 0x04 reset value: 0x00 rrrrrrrr i2st7 i2st6 i2st5 i2st4 i2st3 i2st2 i2st1 i2st0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 bit 7?0 i2st: i 2 c status i 2 c status value status description 0xf0 i 2 c transaction completed successfully. 0xf1 slave address nacked. 0xf2 slave data nacked. 0xf3 i 2 c transaction in progress. 0xf8 i 2 c transaction timed out due to timer configured in i2cto. 0xf9 command?s bytes to transmit byte and data buffer size do not match, or read buffer read number of bytes greater than buffer count. 0xfa i 2 c scl low time-out, using timer configured in i2cto2. 0xfb i 2 c bus free detect has been disabled, and the bus is not free.
CP2120 rev. 0.4 17 6.4. i 2 c receive buffer size bytes received from i 2 c transactions are stored in the 255-byte data buffer. the number of bytes currently stored inside this buffer is saved in the rxbuff internal register. internal register definition 6. rx buff: receive buffer size register 6.5. i 2 c commands spi commands initiate all i 2 c transactions. the CP2120 executes i 2 c transactions only after every byte of the command has been successfully received across the spi bus. once the CP2120 has completed the i 2 c transaction prompted by th e command, the int pin will be pulled low to indicate that command execution has completed. if an i 2 c command is issued while an i 2 c command is in progress, the second i 2 c command will be ignored. 6.5.1. write bytes to i 2 c this command transmits data to an i 2 c slave device. the command begins with the command byte (0x00), followed by the number of bytes to be transmitted across i 2 c, which can range from 1 to 255, and the address of the i 2 c slave. the spi master then sends the data to be transmitted across i 2 c. sending more or fewer bytes than was indicated by the second byte of th e command will result in an error conditio n, and the i2c transaction will not be initiated. once the i 2 c transaction completes, the CP2120 pulls the int pin low and sets the internal register according to the results of the transaction. 6.5.2. read bytes from i 2 c this command attempts to retrieve bytes from an i 2 c slave device. the command begins with the command byte, 0x01, followed by the number of bytes to read (1 to 255) and the address of the i 2 c slave device. once the i 2 c transaction completes, the CP2120 pulls the int pin low and sets i2cstat according to the results of the transaction. the CP2120 saves the number of bytes st ored in the buffer in the internal register named rxbuff. a read buffer command can be issued to retrieve the bytes from the buffer. note that if the spi master issues a second read bytes from i 2 c command before issuing a read buffer command, the bytes stored in the CP2120's buffer will be overwritten. internal register address: 0x06 reset value: 0x00 bit 7-0: rxb7-0: receive buffer size indicates the number of bytes received during the last i 2 c read transaction. rrrrrrrr rxb7 rxb6 rxb5 rxb4 rxb3 rxb2 rxb1 rxb0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 data byte1 data byte n number of bytes command 0x00 slave address +w ... spi master number of bytes command 0x01 slave address +r spi master
CP2120 18 rev. 0.4 6.5.3. read buffer the read buffer command retrieves bytes from the CP2120's data buffer. the command begins with the command byte, 0x06. after the command byte, the spi master must transmit a single byte of data, which is ignored by the CP2120. after receiving the ignored byte of data, the CP2120 transmits data bytes across the miso pin. it is recommended that the spi master read the rxbuff internal register to determine how many bytes are stored in the CP2120's buffer before issuing a read buffer command. if the spi master attempts to retrieve more bytes than the buffer contains, the cp212 0 will signal the error in i2cstat. if an spi master atte mpts to retrieve fewer bytes than are stored in the data buffer, all bytes left in the buffer will be deleted when the read buffer command terminates. 6.5.4. read after write the read after write command writes bytes to one i 2 c slave and then reads bytes from another i 2 c slave. the spi master calls this command by first sending the comma nd byte, 0x02, then the number of bytes to write (1 to 255) and bytes to read (1 to 255). these bytes are followed by the address of the i 2 c slave to which the CP2120 will attempt to write bytes, followed by the data bytes to write. the la st byte of the command is the i 2 c slave from which the CP2120 will attempt to read bytes. 6.5.5. write after write the write after write command writes to an i 2 c slave device and then issues another write to a second i 2 c slave device. the command begins with the command byte, 0x08, fo llowed by the number of bytes to write to the first i 2 c device and the bytes to write to the second i 2 c device. the spi master sends the slave address of the first i 2 c device and the data bytes to write to the first i 2 c slave. the spi master then sends the slave address of the second i 2 c slave device followed by the data byte s to transmit to that slave device. 6.5.6. write to multiple slaves the write to multiple slaves command allows an spi master to write the same data buffer to multiple i 2 c slaves. the command begins with the command byte, 0x09, followed by the size of the data buffer (0 to 255), followed by the number of slaves (0 to 254). next, the list of slave addresses is transmitted. following that, the data buffer to write to each slave is transmitted. the combined size of the slave address list and the data buffer should not exceed 255 bytes. the i2cstat internal register shows the results from the last i 2 c transaction of the command. command 0x06 don?t care data byte 0 data byte n ... spi master CP2120 number of write bytes 0x02 command slave address+w ... number of read bytes data write byte 0 data write byte n slave address+r spi master number of bytes 1 0x03 command slave 1 address +w ... number of bytes 2 data byte 1 data byte n slave 2 address +w data byte 1 ... data byte n spi master num bytes 0x 09 command slave 0 ... num slaves slave n data byte 0 ... data byte n spi master
CP2120 rev. 0.4 19 7. port i/o the CP2120 offers eight general-purpose port pins that c an be configured as output, i nput, or quasi-bidirectional output by writing to the internal regi sters, ioconfig and ioconfig2. pin state can be updated by writing to the internal register, iostate. reading the iostate internal register will return the current values of each port pin. the port pin, eint, can be configured as an edge-triggered interrupt source by writing to the edgeint internal register. the eit bit sets the interrupt to trigger upon a 0 to 1 or a 1 to 0 logic change on the pin. the bit, eie, enables the pin as an interrupt source. once the interrupt has been configured and enab led, the CP2120 will pull the int pi n low when the port pin's logic value switches to ?1'? or ?0?, depending on the interrupt configuration specified in the eit bit. when an interrupt is triggered, eif in the edgeint inte rnal register is set. reading fr om edgeint will clear the eif bit. internal register definition 7. io config: port i/o configuration internal register address: 0x00 reset value: 0x00 bit 7-6: pcio3.1-pcio3.0: port configuration for gpio pin 3 bit 5-4: pcio2.1-pcio2.0: port configuration for gpio pin 2 bit 3-2: pcio1.1-pcio1.0: port configuration for gpio pin 1 bit 1-0: pcio0.1-pcio0.0: port configuration for gpio pin 0 these bits select the port state for gpio pins 3 through 0. r/w r/w r/w r/w r/w r/w r/w r/w pcio3.1 pcio3.0 pcio2.1 pcio2.0 pcio1.1 pcio1.0 pcio0.1 pcio0.0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 pciox.1 pciox.0 gpio pin x mode 0 0 open drain output 0 1 input only 1 0 push-pull output 1 1 input only
CP2120 20 rev. 0.4 internal register definition 8. ioco nfig2: port i/o configuration 2 internal register definition 9. iostate: port i/o state internal register address: 0x07 reset value: 0x00 bit 7-6: pcio7.1-pcio7.0: port configuration for gpio pin 7 bit 5-4: pcio6.1-pcio6.0: port configuration for gpio pin 6 bit 3-2: pcio5.1-pcio5.0: port configuration for gpio pin 5 bit 1-0: pcio4.1-pcio4.0: port configuration for gpio pin 4 these bits select the port state for gpio pins 7 through 4. r/w r/w r/w r/w r/w r/w r/w r/w pcio7.1 pcio7.0 pcio6.1 pcio6.0 pcio5.1 pcio5.0 pcio4.1 pcio4.0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 pciox.1 pciox.0 gpio pin x mode 0 0 open drain output 0 1 input only 1 0 push-pull output 1 1 input only internal register address: 0x01 reset value: 0x00 bit 7-0: gpio7-0: general purpose input/output state write - output appears on output pins. 0: gpiox set to logic low output. 1: gpio set to logic high output. read - reads port state. 0: gpiox is logic low. 1: gpiox is logic high. r/w r/w r/w r/w r/w r/w r/w r/w gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0
CP2120 rev. 0.4 21 internal register definition 10. edgei nt: edge triggered interrupt enable internal register address: 0x08 reset value: 0x00 bit 7: eif: edge triggered interrupt flag 0: no edge triggered event has occurred on the ei_int pin. 1: edge-triggered event has occurred on the ei_int pin. bit 6: eie: edge tri ggered interrupt enable 0: edge triggered interrupts disabled. 1: edge triggered interrupts enabled. bit 5: eit: edge triggered interrupt trigger 0: interrupt triggered on negative-to-posit ive digital transition on the ei_int port pin. 1: interrupt triggered on positive-to-negat ive digital transition on the ei_int port pin. bit 4?bit 0: not used. r/w r/w r/w r/w r/w r/w r/w r/w eif eie eit rsvd rsvd rsvd rsvd rsvd bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0
CP2120 22 rev. 0.4 8. CP2120 revision number the CP2120 revision number can be retrieved by first sending the revision number command byte of 0x40 and then transmitting one ?don?t care? transitional byte. t he CP2120 then transmits the two-byte revision number, most significant byte first, in bcd format. for example, a tran smitted byte sequence of ?0x01 0x44? would indicate that the CP2120?s revision number is equal to 1.44. 0x40 command don?t care rev num byte 1 rev num byte 2 spi master CP2120
CP2120 rev. 0.4 23 d ocument c hange l ist revision 0.1 to revision 0.2 ? various small text changes. ? updated 4.1 pin out chart. ? updated 4.2 pin out diagram. ? updated figure 2. spi bus typical connections. ? added table 3. internal register addresses. ? updated all CP2120 command drawings. ? added section 6.1 determining pull-up register values. ? changed appearance of all internal register definition charts. ? changed contents of section 8. CP2120 revision number. revision 0.2 to revision 0.3 ? removed references to power down mode. ? corrected equation 1, ?i2c clock frequency,? on page 13. ? in internal register 4, ?i2cto2: additional i 2 c time outs,? on page 15, changed internal register address to ?0x09?. ? in internal register 5, ?i2cstat: i 2 c status register,? on page 16, changed all bits to ?r? instead of ?r/w? ? in internal register 6, ?rxbuff: receive buffer size register,? on page 17, changed all bits to ?r? instead of ?r/w?. revision 0.3 to revision 0.4 ? updated figure 1. ? updated digital supply voltage in table 2. ? updated figure 3.
CP2120 24 rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and usbxpre ss are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsi bility for any consequences resu lting from the use of information included herein. additionally, silicon laborator ies assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of the application or use of any pr oduct or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages . silicon laboratories products are not de signed, intended, or authorized for use in appli- cations intended to support or sustain life, or for any other application in which the failure of the silicon laboratories prod uct could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such u nintended or unauthorized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of CP2120

	To Download CP2120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .